This International Standard specifies the logical specifications of STbus which is a highperformance and highly reliable system bus. STbus adopts a synchronous transfer method with a high-speed clock and a split transfer method enabling to minimize bus holding time during one bus operation and to use a bus efficiently. The contents given in this specifications are as follows: a) System bus interface signal provisions; b) Bus operations and transfer protocol for each bus operation; c) Copyback cache coherency control for maintaining consistency between a shared memory and a cache memory of each processor in a multiprocessor system; d) Fault detection function using parity check and duplex configuration for control signals.